Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
The prior art includes a common technique for programming a flash memory cell. In the prior art technique, a high voltage is applied on the drain of the memory cell, a bias voltage on the control gate of the memory cell, and a bias current on the source of the memory cell. The programming essentially places electrons on the floating gate of the memory cell. This is described in U.S. Pat. No. 7,990,773, “Sub Volt Flash Memory System,” by Hieu Van Tran, et al, which is incorporated herein by reference.
An example of prior art circuitry for providing the bias current applied to the source of each memory cell is shown in FIG. 1. Flash memory system 10 comprises flash memory array 30, horizontal decoder 20, and vertical decoder 50. Horizontal decoder 20 selects the row (often called the word line) within flash memory array 30 to be read or written, and vertical decoder 50 selects the column (often called the bit line) within flash memory array 30 to be read or written. Vertical decoder 50 comprises a series of multiplexers coupled to flash memory array 30. Flash memory array 30 comprises N blocks of cells, and each block is coupled to one multiplexer within vertical decoder 50. Current source 40 is coupled to N current mirrors, current mirror 601 through current mirror 60N.
One drawback of the prior art method of programming flash memory cells is that current mirrors, such as current mirrors 601 through 60N, often are mismatched due to natural variations and manufacturing variances, and in large chips, the ground potential also might vary. As a result, during operation the current mirrors actually may draw less or more current than they are supposed to draw.
What is needed is an improved method and apparatus for programming flash memory cells, particularly advanced nanometer flash memory cells, that reduces or eliminates the variability among the bias current sources used during the programming process.